FPGA (Field Programmable Logic Grid Array) has high flexibility and is ideal for various applications such as smart network cards and telecommunication networks. AMD (formerly known as Xilinx) released the latest Versal FPGAs on the 27th, which are designed to be simulated and tested before the chip is built.
Rob Bauer, senior product line manager of the AMD Versal series, pointed out that through these FPGAs, chip designers can create digital twins or digital versions of ASICs or SOCs that are about to be completed before the chips go offline (tapeout), which helps designers verify and Start software development earlier, etc.
This will only become more difficult for chipmakers as advanced packaging technologies transition to 2.5D and 3D chip architectures, Bauer noted. Chip designers no longer do verification and software development for single-chip devices, but multi-chip devices.
This is also AMD's positioning of its Versal Premium VP1902. The chip measures about 77×77mm, has 18.5 million logic units, twice that of the upcoming VU19P, a dedicated Arm core for control plane operations, and an onboard network to assist in debugging.
AMD VP1902 is scheduled to provide samples to customers in the third quarter, and will be fully available in early 2024.
However, simulating a modern SoC with billions of transistors is quite resource-intensive. AMD said that depending on the size and complexity of the chip, it may need to span multiple racks and dozens or even hundreds of FPGAs.
While AMD's newest FPGAs are primarily aimed at chipmakers, AMD says the chips are also well-suited for companies engaged in firmware development and testing, IP block and subsystem prototyping, peripheral verification, and other test cases.
As for compatibility, the new chip will utilize the same underlying Vivado ML software development kit as the FPGA. AMD said it will work with leading EDA suppliers such as Cadence, Siemens and Synopsys to increase support for more advanced features.